1. Field of the Invention
The present invention generally relates to measuring a depth of a Through-Silicon-Via (TSV) during in-line semiconductor fabrication before the TSV is filled with conductive material.
2. Description of the Related Art
Within silicon-based semiconductor manufacturing techniques there is no in-line measurement method available prior to metal fill/wafer grinding/BSM deposition to determine the TSV yield. In other words, the TSV yield determination can only be obtained after the BSM deposition, and thus any poor yields cannot be recovered before the end of entire fabrication process.
Through-Silicon-Vias (TSVs) are not electrically functional before wafer thinning and back-side-metal (BSM) deposition, and therefore the conventional in-line electrical test cannot be used to determine the yield of the TSVs in a timely fashion before being filled with conductive material. In other words, the yield determination can only be detected after the TSVs are filled with conductive material, and thus any poor yields cannot be recovered once filled with a conductive material.
There exists a need to provide a test to determine the depth of TSVs before they are filled with conductive material so that if the TSVs are determined to be inadequately formed in depth, the semiconductors may be re-etched to improve the yield before being filled with conductive material.